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Figure 15.8. I C Master Transmitter/Slave Receiver with 10-bit Address
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When a slave receives a 10-bit address, it must acknowledge both the address bytes if they match the
address of the slave.
When performing a master transmitter operation, the master transmits the two address bytes and then
the remaining data, as shown in Figure 15.8 (p. 148) .
2
S
ADDR (1st 7 bits)
W A
Addr (2nd byte)
A
DATA
A
P
Figure 15.9. I C Master Receiver/Slave Transmitter with 10-bit Address
When performing a master receiver operation however, the master first transmits the two address bytes
in a master transmitter operation, then sends a repeated START followed by the first address byte and
then receives data from the addressed slave. The slave addressed by the 10-bit address in the first two
address bytes must remember that it was addressed, and respond with data if the address transmitted
after the repeated start matches its own address. An example of this, with one byte transmitted is shown
in Figure 15.9 (p. 148) .
2
S
ADDR (1st 7 bits)
W A
Addr (2nd byte)
A Sr
ADDR (1st 7 bits)
R
A
DATA
N
P
Arbitration is supported by the I C module for both masters and slaves. Clock synchronization and clock
The I C is enabled by setting the EN bit in the I2Cn_CTRL register. Whenever this bit is cleared, the
internal state of the I C is reset, terminating any ongoing transfers.
15.3.1.5 Arbitration, Clock Synchronization, Clock Stretching
Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration
occurs when two devices try to drive the bus at the same time. If one device drives it low, while the
other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain
bus configuration. Both devices sample the bus, and the one that was unable to drive the bus in the
desired direction detects the collision and backs off, letting the other device continue communication
on the bus undisturbed.
Clock synchronization is a means of synchronizing the clock outputs from several masters driving the
bus at once, and is a requirement for effective arbitration.
Slaves on the bus are allowed to force the clock output on the bus low in order to pause the
communication on the bus and give themselves time to process data or perform any real-time tasks they
might have. This is called clock stretching.
2
stretching is also supported.
15.3.2 Enable and Reset
2
2
When Re-enabling the I C, the ABORT command or the Bus Idle Timeout feature must be
Note
2
The I C slave is partially asynchronous, and some precautions may be necessary to always ensure a
applied prior to use even if the BUSY flag is not set.
15.3.3 Safely disabling and changing slave configuration
2
safe slave disable or configuration change. If the user cannot guarantee that an address match will not
occur at the exact time of slave disable or slave configuration change while the slave is enabled, these
measures should be made.
Worst case consequences for an address match while disabling slave or changing configuration is that
the slave may end up in an undefined state. To reset the slave back to a known state, the EN bit in
2011-04-12 - d0001_Rev1.10
148
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